ADM1027
ABSOLUTE MAXIMUM RATINGS*
Positive Supply Voltage (V
CC
) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on 12 V
IN
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Voltage on Any Other Input or Output Pin . . . . 0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . . ? mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . . ?0 mA
Maximum Junction Temperature (T
J MAX
) . . . . . . . . . . 150rC
Storage Temperature Range . . . . . . . . . . . . . 65rC to +150rC
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215rC
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200rC
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
ADM1027
TACH2
TACH1
PWM2/SMBALERT
TACH3
VID3
SDA
SCL
GND
V
CC
VID2
VID1
VID0
PWM3/ADDRESS ENABLE
TACH4/ADDRESS SELECT
D2
D2+
D1
PWM1/XTO
V
CCP
2.5V
IN
12V
IN
D1+
VID4
5V
IN
THERMAL CHARACTERISTICS
24-Lead QSOP Package:
q
JA
= 123rC/W, q
JC
= 27rC/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM1027 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P
S
t
SU; DAT
t
HIGH
t
F
t
HD; DAT
t
R
t
LOW
t
SU; STO
P
S
SCL
SDA
t
HD; STA
t
HD; STA
t
SU; STA
t
BUF
Figure 1. Diagram for Serial Bus Timing
Rev. 3 | Page 4 of 56 | www.onsemi.com
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